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Short Desc. : PLB EMAC (DO-DI-10-100-EMAC-SD)
Overview :
The PLB Ethernet 10/100 Mbs Media Access Controller (PLB_EMAC) with interface to the Processor Local Bus (PLB) has been designed incorporating the applicable features described in IEEE Std. 802.3 MII interface specification. The IEEE Std. 802.3 MII interface specification is referenced throughout this document and should be used as the authoritative specification. Differences between the IEEE Std. 802.3 MII interface specification and the Xilinx EMAC implementation are highlighted and explained in the Specification Exceptions.
Features : - 64-bit PLB master and slave interfaces.1
- Memory mapped direct I/O interface to registers and FIFOs as well as Simple DMA and Scatter/Gather DMA capabilities for low processor and bus utilization.
- Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
- IEEE 802.3-compliant MII and management control writes and reads with MII PHYs plus a programmable PHY reset signal
- Supports auto-negotiable and non auto-negotiable PHYs for 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs at full or half duplex
- Independent internal TX and RX FIFOs (2K - 32K) for holding data for more than one packet. 2K byte depth is sufficient for normal 1518 maximum byte packets but 4K byte depth provides better throughput.
Categories :
Portability :
Type : Soft
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