Login

 Xilinx 
Short Desc. : OPB IIC Bus Interface (DO-DI-IIC-SD)
Overview :
The IIC bus interface soft IP core communicates with other devices on the OPB (On-Chip Peripheral Bus). It includes the Master and Slave Controller and supports the following features: Master or Slave operation, multi-master operation, software selectable acknowledge bit, arbitration lost interrupt with automatic mode switching from Master to Slave, calling address identification interrupt with automatic mode switching from Master to Slave. The core supports all features specified in the Philips IIC specification v2.1, except the high-speed mode. The IIC core can be parameterized for customer specific applications. An evaluation version of this core is available with the Embedded Development Kit (EDK).
Features : - Master or Slave operation
- Multi-master operation
- Software selectable acknowledge bit
- Arbitration lost interrupt with automatic mode switching from Master to Slave
- Calling address identification interrupt with automatic mode switching from Master to Slave
- START and STOP signal generation/detection
- Repeated START signal generation
- Acknowledge bit generation/detection
- Bus busy detection
- Fast Mode 400 KHz operation or Standard Mode 100 KHz
- 7 Bit or 10 Bit addressing
- General Call Enable or Disable
- Transmit and Receive FIFOs - 16 bytes deep
- Throttling
- General Purpose Output, zero to 8 bits wide
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy