Short Desc. : PLB 16550 UART (DO-DI-UART-SD)
Overview :
This document provides the specification for the PLB Universal Asynchronous Receiver/Transmitter (UART) Intellectual Property (IP). The UART described in this document has been designed incorporating the features described in National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995),
Features : - Hardware and software register compatible with all standard 16450 and 16450 UARTs
- Implements all standard serial interface protocols
- 5, 6, 7, or 8 bits per character
- Odd, Even, or no parity detection and generation
- 1, 1.5, or 2 stop bit detection and generation
- Internal baud rate generator and separate receiver clock input
- Modem control functions
- False start bit detection and recovery
- Prioritized transmit, receive, line status, and modem control interrupts
- Line break detection and generation
- Internal loop back diagnostic functionality
- Independent 16 word transmit and receive FIFOs
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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