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 Xilinx 
Short Desc. : OPB ATMC (DO-DI-ATM)
Overview :
The OPB ATMC Design soft IP core is designed for Xilinx FPGAs with a UTOPIA L2 interface that is attached to the On-Chip Peripheral Bus (OPB). The core supports several of the features defined in UTOPIA L2 v1.0 as written by the ATM forum technical committee. The core is specified to operate at an interface frequency between 10 and 40 MHz with a system operating of 125 MHz through the OPB interface. An evaluation version of this core is available with the Embedded Development Kit.
Features : - UTOPIA Level 2 master or slave interface
- UTOPIA interface data path of 8 or 16 bits
- Interface throughput up to 622 Mbps (OC12)
- Single channel VPI/VCI service and checking in received cells
- Header error check (HEC) generation and checking
- Parity generation and checking
- IP interface frequency of 10 MHz to 40 MHz
- System operating frequency up to 125 MHz through OPB interface
- OPB interface including register, FIFO, DMA, and scatter gather capabilities
- Statistics gathering of short cells, long cells, unknown VPI/VCI, parity errors, and HEC errors
- Selectively prepend headers to transmit cells
- Selectively pass entire received cells or payloads only
- Selectively transfer 48 byte ATM payloads only
- Loop back test mode
- Auto processing or discard of short received cells, parity errored cells, unknown VPI/VCI, or HEC errored cells
Categories :
Portability :
Type : Soft
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