Part Number : Multi-Channel-OPB_DDR2_Controller
Overview :
The Xilinx Multi-Channel On-chip Peripheral Bus Double Data Rate Synchronous DRAM (MCH OPB DDR2 SDRAM) controller for Xilinx FPGAs provides a DDR2 SDRAM controller that connects to the OPB and multiple channel interfaces and provides the control interface for DDR2 SDRAMs. It is assumed that the reader is familiar with DDR2 SDRAM and the MCH protocol.
Features : - Parameterizable number of channel (MCH) interfaces that can be configured with the Xilinx Cachelink (XCL) protocol
- Optional OPB interface & indeterminate burst support
- Performs device initialization sequence upon power-up and reset conditions for ~200 us
- Performs auto-refresh cycles
- Supports DDR2 SDRAM self refresh mode
- Supports CAS latencies of 3, 4 and 5
- Supports target word first XCL cacheline transactions of 1, 4, 8 and 16 words
- Supports 16-bits, 32-bits and 64-bits DDR2 SDRAM devices
- Supports multiple (up to 4) external DDR2 memory banks
- Selectable On Die Termination (ODT)
- Supports DDR2 burst size of 4
- Supports differential DQS
- Capable to separate DDR2 clock frequency domain from MCH/OPB clock frequency domain. Following combinations of frequencies are tested:
- MCH/OPB clock: 66 MHz & DDR2 clock: 133 MHz
- MCH/OPB clock:100 MHz & DDR2 clock: 133 MHz
- MCH/OPB clock:100 MHz & DDR2 clock: 200 MHz
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy