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 Xilinx 
Part Number : Multi-Channel-OPB_DDR_Controller
Overview :
The Xilinx Multi-CHannel (MCH) On-chip Peripheral Bus (OPB) Double Data Rate Synchronous DRAM (SDRAM) controller for Xilinx FPGAs provides a DDR SDRAM controller which connects to the OPB and multiple channel interfaces and provides the control interface for DDR SDRAMs. It is assumed that the reader is familiar with DDR SDRAM and MicroBlaze.
Features : - Parameterizable number of channel (MCH) interfaces that can be configured with the Xilinx Cachelink (XCL) protocol (see "Reference Documents" on page 36)
- Optional OPB interface
- Performs device initialization sequence upon power-up and reset conditions for ~200uS. Provides a parameter to adjust this time for simulation purposes only Performs auto-refresh cycles
- Supports DDR SDRAM self refresh mode
- Supports CAS latencies of 2 or 3 set by a design parameter
- Supports target word first XCL cacheline transactions of 1, 4, 8 and 16 words
- Supports 16, 32 and 64-bits DDR data widths set by a design parameter
- Supports multiple (up to 4) DDR memory banks
- Allows DDR SDRAM open row management set by a design parameter
- Supports capability to separate DDR clock domain from the MCH/OPB bus clock domain set by a design parameter for the following frequency combinations:
- MCH/OPB clock: 50 MHz & DDR clock: 100 MHz
- MCH/OPB clock: 66 MHz & DDR clock: 133 MHz
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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