Short Desc. : PLB DDR SDRAM Controller
Overview :
The PLB DDR SDRAM controller soft IP core connects to the PLB bus and provides the control interface for DDR SDRAMs. Other features include performing device initialization sequence upon power-up and reset conditions, auto-refresh cycles. It also supports single-beat and burst transactions, target-word first cache-line transactions, cacheline latencies of 2 or 3 set by a design parameter, and various DDR data widths set by a design parameter. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
Features : - Used to design high-performance embedded systems using PowerPC core in Virtex-II Pro FPGAs
- Also performs device initialization sequence upon power-up and reset conditions
- Parameterizable to specific customer needs and application
- Interface between PLB bus and DDR SDRAM
Categories :
Portability :
Type : Soft

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