Login

 Xilinx 
Short Desc. : PLB SDRAM Controller
Overview :
The PLB SDRAM controller provides a SDRAM controller that connects to the PLB bus and provides the control interface for SDRAMs. The core offers designers the following features: PLB interface that can be used to perform device initialization sequence upon power-up and reset conditions, auto-refresh cycles. The core also supports single-beat and burst transactions, target-word first cache-line transactions, cacheline latencies of 2 or 3 set by a design parameter and various SDRAM data widths set by a design parameter. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
Features : - Used to design high-performance embedded systems using PowerPC core in Virtex-II Pro FPGAs
- Connects to the PLB bus and provides control interface for SDRAMs
- Parameterizable to specific customer needs and application
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy