Short Desc. : OPB DDR SDRAM Controller
Overview :
The Xilinx On-chip Peripheral Bus Double Data Rate (OPBDDR) Synchronous DRAM (SDRAM) controller that connects to the OPB and provides the control interface for DDR SDRAMs. It is assumed that the reader is familiar with DDR SDRAMs and the IBM PowerPC™.
Features : - OPB interface
- Performs device initialization sequence upon power-up and reset conditions for ~200uS. Provides a parameter to adjust this time for simulation purposes only
- Performs auto-refresh cycles
- Supports CAS latencies of 2 or 3 set by a design parameter
- Supports 16, 32 and 64 bits DDR data widths set by a design parameter
- Supports indeterminate burst length
- Provides big-endian connections to memory devices, See Connecting to Memory for details on memory connections
- Supports multiple (up to 4) DDR memory banks
- Supports capability to separate DDR clock frequency from OPB clock frequency for the tested values
Categories :
Portability :
Type : Soft
TrueCircuits: IoTPLL

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