Short Desc. : Device Control Register Bus (DCR)
Overview :
The 32-bit Device Control Register Bus (DCR) IP core provides the DCR bus structure as described in the IBM 32-Bit Device Control Register Bus (DCR) Architecture Specification to allow easy connection of the DCR Master to the DCR slaves. It provides the daisy-chain for the DCR data bus and the OR gate for the DCR acknowledge signals from the DCR slaves.
Features : - DCR connections for one DCR master and a variable number of DCR slaves, which are configurable via design parameter
- Daisy-chain connections for the DCR data bus
- Required OR function of the DCR slaves’ acknowledge signal
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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