Login

 Xilinx 
Short Desc. : Processor Local Bus (PLB)
Overview :
The 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write and read data path units with a three-cycle-only arbitration feature. It contains a DCR slave interface to provide access to its bus error status registers. It also contains a power-up reset circuit to insure that a PLB reset is generated if no external reset has been provided. The PLB consists of a central bus arbiter, the necessary bus control and gating logic, and all necessary bus OR/MUX structures. The PLB provides the entire PLB bus structure and allows for direct connection for up to 16 masters and 16 slaves. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
Features : - Based on the IBM 64-bit PLB architecture specification
- Used to develop high-performance embedded systems using PowerPC core in Virtex-II Pro
- Provides complete PLB bus structure
Categories :
Portability :
Type : Soft
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy