Short Desc. : OPB to PLB Bridge
Overview :
The On-chip Peripheral Bus (OPB) to Processor Local Bus (PLB) Bridge module translates OPB transactions into PLB transactions. It functions as a slave on the OPB side and a master on the PLB side. Access to the control register and bus error status registers is user selectable from either the OPB or an optional DCR interface. The OPB to PLB Bridge is necessary in systems where an OPB master device (such as a DMA engine or an OPB based co-processor) requires access to PLB devices (i.e., high-speed memory devices, etc.). The OPB to PLB Bridge design allows the customer to tailor the bridge to suit their application by setting certain parameters to enable/disable features. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
Features : - One of the infrastructure cores available in the Embedded Development Kit (EDK)
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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