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Short Desc. : MPEG4 Simple Profile Decoder
Overview :
The Xilinx MPEG-4 Part 2 Simple Profile Decoder core is a fully functional VHDL design implemented on a Xilinx FPGA. The MPEG-4 core accepts compressed video information and recreates a video image suitable for display based on the “Information Technology–Generic Coding of Audio Visual Objects-Part 2 Visual” section of the ISO/IEC 144962-2 standard.
Features : - Supported FPGA families: Supported FPGA families: Virtex®-5, Virtex-4, Virtex-II Pro, Virtex- II, Spartan®-3, and Spartan-3A
- MPEG-4 Part 2 Simple Profile standard
- Maximum frame size for standard TV resolutions
- IDCT-based transform
- Macroblock processing
- 4:2:0 YUV processing
- Motion compensation Residual processing
- 8-bit input data
- 12-bit IDCT coefficients
- AC/DC prediction
- Variable length decoder
- Local YUV buffer
- Communication primitives
- Bit-accurate testing
- I and P Frame Processing
Categories :
Portability :
Type : Soft
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