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 HDL Design House 
Short Desc. : HIP 4000 Golay Encoder/Decoder IP Core
Overview :
The use of IP cores in ASIC, FGPA and system-on-chip (SoC) design has become a critical methodology as companies struggle to address the need for rapid prototyping and production. Reusable, drop-in components with pre-defined
functionality, IP cores speed the design cycle, improve design quality, and allow a greater degree of innovation, enabling companies to reduce design costs and create market differentiation.
Features : - • Support perfect Golay (23,12) and quasiperfect (24,12) binary code
- • 3 bits error detection and correction
- • Low latency
- • Single clock synchronous design
- • Technology independent HDL code
Categories :
Portability :
Type : Soft
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