Mentor Graphics 
Short Desc. : PCI Express to AMBA 3 AXI Bridge IP
Overview :

Design challenges are greatly increased when a bridge is required
between two sophisticated PCI Express (PCIe) and AMBAbus protocols.
A bridge enables higher data throughput and allows multiple system buses
to be configured at both ends. Realizing the need of this design challenge,
Mentor Graphics created the PCIe to AMBA3 AXI bridge IP in conjunction
with Mentor’s PCIe controller IP to provide the end-to-end connectivity
between AMBA3 AXI bus to PIPE-compliant PCIe PHY.

Features : - Fully integrated with Mentor’s PCIe controller
- Allows PCIe to be dynamically configured for Root Port or Endpoint at power-up
- Configurable 32-bit or 64-bit datapath AMBA3 AXI Master/Slave interface
- Local/remote CPU support through concurrent DMA write and read
- Supports MSI or legacy interrupts for PCIe
- Supports system interrupt and error reporting for ARM processors
- Supports 32b and 64b addressing from PCIe to AMBA3 AXI bus
- User programmable address translation between AMBA3 AXI and PCIe in both EP and RC mode
- Built-in EEPROM support
- Capable of queuing up to 8 transactions concurrently for high throughput
- Supports all power management states L0, L0s, L1, L2 & L3
- Clock request (Clkreq) mechanism for low power mode in mobile form
- factors
- Supports all required and optional PCIe power management features
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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