||- Pre-synthesis configuration to support 1Gbps – 40Gbps.
- Synthesized up to 200Mhz for FPGA and 300Mhz on ASIC
- Throughput is determined by clock-frequency x WW (word width), providing the best synthesis characteristics.
- Pre-synthesis configuration of WW to be 8xN bits (N = any number from 1 to 32)
- Minimal RAM resources - single dual port RAM of 256B.
- Supporting variable code-word length (N) up to 255Bytes (including shortened code-words).
- Capability to correct up to 8 bytes-errors in a codeword.
- Capability to detect uncorrectable code word, when number of errors exceeds the correction capability.
- Minimal decoder latency – 271 clock cycles.
- Flow-control support.
- Various counters used for statistics and BER monitoring.
- Single clock design, standard cells, registered I/Os.
- Proved to provide the theoretical performance.
- Same design used for FPGA and ASIC (excluding RAM models).
- Optional gated-clock design for minimal Power consumption characteristics