Aliathon Ltd 
Short Desc. : E1/T1/J1 Framer Core
Overview :
Aliathon’s E1/T1/J1 Framer core provides a flexible, resource-efficient, programmable-logic based solution
for level 1 PDH interfacing.
Features : - Performs frame generation for the following level 1 PDH signals...
- o T1 - Extended Super-frame (ESF)
- o T1 - Super-frame (SF)
- o T1 - Ft framing only
- o J1
- o SLC-96
- o E1 (no CRC)
- o E1 (CRC-4)
- Calculates and inserts CRC values for T1 (ESF), J1 and E1
- Provides a frame overhead insertion interface.
- Implements a byte-wide frame-aligned payload input interface.
- Generates multiple output streams, making it ideal for interfacing to SONET/SDH Mappers or multichannel LIUs.
- The output data streams may dynamically range between 1 and 8 bits wide, allowing seamless interfacing to SONET/SDH VC11 and VC12 mappings
- Interfaces to other Aliathon cores, such as SONET/SDH Mappers, E2/T2 Channelised Framers and ATM/HDLC Framers to provide complete SDH/PDH solutions.
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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