Short Desc. : Low-cost 12bit, 80MS/s Nyquist-Rate DAC
Overview :
The cell is a complete high-performance fully differential high speed current-steering DAC core designed for 0.13mm 1P6M CMOS technology with MiM capacitors. The converter has a segmented architecture with 4 binary bits and 8 thermometer bits which guarantees a good accuracy-active area trade-off.

It achieves 71dB SNDR at sampling rates up to 80MS/s with optimized power dissipation. The cell also features high tolerance to gradient mismatch effects through the use of an efficient switching sequence algorithm. No calibration circuitry is required.

The reference current is generated on-chip from an internal bandgap reference.

A power-down mode is available for very low current consumption when the cell is inactive. A stand-by mode with reduced power consumption is also available for fast start-up. The DAC core occupies approximately 1.25mm2 silicon area.
Features : - 0.13um 1P6M (1.2V/3.3V) - without MiM capacitors.
- 12bit digital input
- 80MS/s conversion rate
- 71dB SNDR @ Nyquist rate
- 86dB SFDR @ Nyquist rate
- 1.0V peak-to-peak output signal range (25W termination)
- Dual power supply 3.3V / 1.2V (±10%)
- On-chip bandgap and reference current generation
- Power-down capability
- Low-power consumption: 130mW @ 80MS/s
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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