Aeluros, Inc. 
Short Desc. : XAUI PHY IP Core
Overview :
The Aeluros XAUI IP core (implemented and verified in the Puma AEL100x family of products) presents a robust implementation, able to drive 40” of standard FR4 material and 2 connectors, more than enough distance for backplane systems. The incorporation of programmable output swing capabilities and a programmable transmit equalization feature ensures support across extended channels, or even for shorter distances, depending on customer requirements.
Features : - Compliant with IEEE802.3ae XAUI spec
- Compliant with INCITS/T11 10GFC spec
- Wide frequency range, 1 – 4 Gbps
- Power-efficient design (320 mW)
- Adjustable transmit pre-emphasis
- More than 40in FR4 with pre-emphasis
- Programmable I/O polarity
- Programmable lane ordering
- PRBS generator and checker
- Internal loop-back feature
- Modular implementation
- 0.13μm TSMC CMOS process
Categories :
Portability :
Type : Soft
CST: Webinars Begin on February 9
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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