Aeluros, Inc. 
Short Desc. : PCI Express PHY IP Core
Overview :
The Aeluros PCI Express PHY IP Core incorporates the 2.5 Gbps I/O, serializer/deserializer and full PHY Interface for PCI Express (PIPE) parallel interface functions. In addition, an extensive collection of features like power management mode support, multiple loopback paths, beacon signaling, hot plug implementation, and receiver detection are all included.
Features : - Compliant with PCIe base spec Rev 1.0a
- TSMC 0.13μm (1.2V/2.5V) process
- PIPE 1.0 compliant parallel interface
- Spread spectrum clocking support
- Programmable output swing
- Power down mode (P0, P0s, P1, P2)
- Programmable termination resistor
- Beacon out-of-band signaling
- Receiver detection sequence
- Receiver sensitivity ~ 65mV
- Max power = 92 mW/channel (P0)
- Parallel & serial loopbacks
- Compact design (.77 x 1.1mm, with I/Os)
- Hot-Plug capability
- Reference frequencies from 25 – 200MHz
Categories :
Portability :
Type : Soft

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