Advanced Architectures 
Short Desc. : A2FP Floating Point Coprocessor
Overview :
The A2FP is a fully synthesizable module implemented in Verilog RTL. It is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE Standard). It is designed to provide high performance floating-point computation while minimizing die size and power. Pipelined, single-cycle throughput operation is available for all operations except FDIV, FREM & FSQRT.
Features : - User selectable precision
- o Single precision only
- o Single & Double precision
- Fast Hardware execution of primary math functions
- Full IEEE compliance in hardware
- Fast Mode only with full IEEE compliance via software support
- Low gate count to minimize power
- Extendible to run complex math functions with the addition of a sequencer and ROM
- Primary functions
- o FADD Add
- o FSUB Subtract
- o FCMP Compare
- o FMUL Multiply
- o FDIV Divide
- o FREM Remainder
- o FSQRT Square Root
- Conversions
- o FCIS Integer to Single Precision
- o FCSI Single Precision to Integer
- o FCID Integer to Double Precision
- o FCDI Double Precision to Integer
- o FCSD Single to Double
- o FCDS Double to Single
- Support Functions
- o FCHS Change Sign
- o FABS Absolute Value
- o FLOGB Extract exponent
- o FRINT Round to nearest
- Control / Status Register controls all modes of operation
- o Compliance mode (full IEEE)
- o Fast mode without traps
- o Fast mode with traps
- o Rounding modes
- o Exception Masking
- Flag outputs to support conditional branching or conditional execution
- Full verification Suite
- o Enhanced IEEE 754 Compliance Checker
- o Assembly Code level tests
Categories :
Portability :
Type : Soft
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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