Faraday Technology Corp. 
Overview :
This library is tailored for UMC’s 0.18μm 1.8V Generic II Logic Process. It is
especially suitable for high speed / high density applications. The 9-track (5.04μm)
cell height along with a wide selection of drive strengths enables customers to
implement high performance designs with smallest area. This library can be
customized to provide new cells for customers, following Faraday’s internal
evaluation procedures.
Features : - UMC’s 0.18μm 1.8V GenericII Logic Process
- Raw gate density: 110,000 gates/mm2 offers high density needed for low cost applications
- Wide drive strength range and optimized P/N ratio for performance
- Complete set of models for industry-standard EDA tools
- Support arithmetic cells for data-path designs
- Full set of gated clock buffers for power saving
- Only Metal 1 used in layout, each cell has at least one sub / well contact
- Flexible row abutment
- Built-in decoupling capacitance to aid IR drop in filler cells
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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