Comtech AHA Corp. 
Part Number : AHA4701
Short Desc. : 30 Mbits/sec LDPC Encoder/Decoder Core
Features : - Maximum date rate is 30 Mbits/sec for 3/4 code rate in Altera Stratix 30 FPGA
- Block sizes up to 30 Kbits
- Input quantization up to 6 bits
- Programmable up to 256 iterations per block
- Compact, area efficient, low power
- Supports "code-change-on-the-fly" allowing adaptation to changing channel conditions
- Exact code rate matching is possible
- Field re-programmability that supports multiple code rates and block sizes
- Fully synchronous design style
- Configurable design allows trade-offs between error rate performance
- and data rate
- Internal buffering allows flexible data interface
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper

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