ARM Ltd. 
Short Desc. : ARM11 MPCore
Overview :
The ARM11TM MPCoreTM synthesizable processor implements the ARM11 microarchitecture and can be configured to contain between one and four processors delivering up to an aggregate 2600 Dhrystone MIPS of performance
Features : - Highly configurable
- Flexibility of total available performance from implementations using between 1 and 4 processors.
- Sizing of both data and instruction cache between 16K and 64K bytes across each processor.
- Either dual or single 64-bit AMBA 3 AXI system bus connection allowing rapid and flexibility during SoC design
- Optional integrated vector floating point (VFP) unit
- Sizing on the number of hardware interrupts up to a total of 255 independent sources
- Efficient processing
- Rich ARMv6K architecture-based multiprocessor-capable instruction set architecture providing architectural enhancements that further improve performance of a multiprocessor capable OS
- Support for ARM Thumb ® instruction set
- ARM Jazelle technology
- ARM DSP extensions
- SIMD (single instruction, multiple data) media processing extensions delivering up to 2x performance for video processing
- Advanced energy management features
- Designed for low power by providing gate level shutdown of unused resources
- Supporting the ability for each processor to go into standby, dormant or power off energy management states providing control over both the dynamic and static energy consumed by the processor and memories with savings of up to 85%
- Support for dynamic voltage and frequency scaling using technology such as ARM Intelligent Energy Manager (IEM)
- High performance memory system
- 16-64k independent data and instruction cache per processor with support for full data coherence.
- Ability for data to move between each processor’s cache permitting rapid data sharing without accesses to main memory.
- Optimized L1 memory system significantly increasing throughput and further lowering power consumption.
- Fully physical index, physically tagged data cache removing the performance costs from de-aliasing addresses on larger caches or needing to flush caches on an OS context-switch
- Data cache allocation on both read and writes along with an intelligent merging write buffer with forwarding to greatly reduce main memory accesses and significantly increase the ability to form bursts from multiple memory requests.
- Unique 'cork-screw' cache memory design accelerating cache allocation and eviction to a single cycle
- Simple design integration
- ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.
- Integration of the essential system components provides a standard OS view of the key functionality and reduces the complexity and risk associated in gaining OS support.
- Utilizes 64-bit AMBA 3 AXI bus interconnect simplifying system interconnect while providing higher data bandwidth and easier timing closure
- Software support environment
- Standard ARM programming model with support for existing OS, middleware and applications
- Availability of Linux 2.6 SMP capable operating system and tools. Click to download.
- Support for both asymmetric multiprocessor (AMP) workloads, and for symmetric multiprocessing (SMP) multiprocessor programming paradigms
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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