Faraday Technology Corp. 
Part Number : FSA0A_C_T33_LVPECL_IO
Overview :
This library is tailored for UMC’s 0.18μm 1.8V/3.3V Generic II Logic Process. For
high-speed chip-to-chip communications with specified DC drive
characteristics, these differential type receivers and drivers provide data
transfer rates up to 300Mbps. Single-ended type buffers are provided for lower
power consumption. For improved noise performance (due to common mode
noise rejection) these cells provide differential type buffers. Staggered and
In-line structures are provided for all PECL I/O cells to fit pad limit or core
limit designs.
Features : - UMC’s 0.18μm 1.8V/3.3V Generic II Logic Process
- 3.3V PECL I/O cells
- Options for 25 ohms and 50 ohms output buffers
- 300MHz for differential type drivers and receivers
- 250MHz for single-ended type driver and receivers
- Support power down mode
- Built-in Antenna diodes for all pins
- ESD Robustness and Latch-up immunity proven by Silicon
Categories :
Portability :
Type : Hard

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