ARM Ltd. 
Short Desc. : ARM Cortex-A8
Overview :
The ARM Cortex™-A8 processor is based on the ARMv7 architecture and has the ability to scale in speed from 600MHz to greater than 1GHz. The Cortex-A8 processor can meet the requirements for power-optimized mobile devices needing operation in less than 300mW; and performance-optimized consumer applications requiring 2000 Dhrystone MIPS.
Features : - In-order, dual-issue, superscalar microprocessor core
- 13-stage main integer pipeline
- 10-stage NEON media pipeline
- Dedicated L2 cache with programmable wait states
- Global history based branch prediction
- Works in conjunction with a power optimized load store pipeline to deliver 2.0 DMIPS/MHz for power sensitive applications
- ARMv7 architecture compliant including:
- Thumb®-2 technology for greater performance, energy efficiency, and code density
- NEON™ signal processing extensions to accelerate media codecs such as H.264 and MP3
- Jazelle RCT Java-acceleration technology to optimize Just In Time (JIT) and Dynamic Adaptive Compilation (DAC), and reduce memory footprint by up to three times
- TrustZone technology for secure transactions and Digital Rights Management (DRM)
- Integrated Level 2 Cache
- Built using standard compiled RAMs
- configurable size from 0K – 1MB
- Programmable delay
- Optimized Level 1 Caches
- Performance and power optimized
- Combine minimal access latency with hash way determination to maximize performance and minimize power consumption.
- Dynamic Branch Prediction
- Enabled by branch target and global history buffers
- Achieves 95% accuracy across industry benchmarks.
- Replay mechanism minimizes miss-predict penalty
- Memory System
- Single-cycle load-use penalty for access to the L1 cache
- Hash array in the L1 cache limits activation of the memories to when they are likely to be needed.
- Direct interface between the integrated, configurable L2 cache and the NEON media unit for data streaming
- Banked L2 cache design that enables only one bank at a time
- Support for multiple outstanding transactions to the L3 memory to fully utilize the CPU
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy