Faraday Technology Corp. 
Part Number : FOR0G_A33_T33_ANALOGESD_IO
Overview :
This I/O set is designed by using UMC 0.11 μm logic SP (FSG) process. This set provides a full ESD protection for an isolated analog block. 2 layout structures, both optimized for the pad-limited and core-limited designs are available.
Features : - UMC 0.11 μm logic SP (FSG) process
- 3.3 V ESD protection cells for the analog I/Os
- 3.3 V power/ground cells with the ESD protection
- Power-cut cells with the ESD protection to separate the 3.3 V analog blocks from the digital blocks
- ESD robustness and latch-up immunity proven by silicon
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy