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 ASIC Architect, Inc. 
Short Desc. : DDR I/II/III Memory Controller Core
Overview :
ASIC Architect's DDR I/II/III Controller Cores are an integral part of the product portfolio aimed at providing a complete end-to-end solution in the High Speed Interface Controller domain. The DDR controller cores have been architected, designed and verified by ASIC/SoC industry veterans. The add-on solution cores that come with the DDR Controller accelerate the chip-level integration by connecting multiple clients to the DDR Controller.
Features : - Intelligent Bank Management for ensuring maximum utilization and efficiency
- Address Mapping between application bus and row, column & bank address
- Choice of 16/32/64-bit DDR bus-width
- Supports Back-to-Back WR & RD with minimum time intervals
- Supports On-die termination (ODT), and Off-Chip Driver impedance adjustment
- Byte-wide mask support
- Optional ECC support
- Auto initialization of DDR Memories
- Power down control
- Command queuing to maximize the performance on DDR bus
- Fully ATPG Testable - Multiple Clock Domains Application Clock and DDR Clock
- Supports upto 800MHz in DDR 2 Mode & upto 1.6GHz in DDR 3 Mode
- Low gate count and Low latency
- Verified with leading memory and IO vendors
Categories :
Portability :
Type : Soft
Deliverables : - Synthesizable Verilog RTL, Testbench and Models for Simulation
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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