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ASIC Architect, Inc.
Short Desc. :
PCI Express Dual Mode Cores
ASIC Architect's high performance cores come in multiple datapath flavors with the choice of 8-bit or 16-bit PIPE PHY Interface. The cores have been architected to achieve very low latency, high throughput, and quick timing closure with a very small silicon footprint. The user interface provides practical and integration-friendly mechanisms for the integration of the cores to the user logic.
- High Performance with Low Latency, Maximum Throughput, Multiple Pipelined Memory WR/RD capability
- Low Silicon Footprint - Suitable for Multiple Instances of the Core in Single ASIC/FPGA
- Highly Parameterized Core supporting both cut-through and store-and-forward schemes
- Supports operation with 8-bit and 16-bit PIPE interface
- Implements all optional configuration space and capability structures
- Configurable Retry buffering scheme for low footprint and latency
- Supports all power management states L0,L0s,L1,L2 & L3
- Supports PCI Express Advanced Error Reporting
- Synthesizable Verilog RTL, Testbench and Models for Simulation, Sample Synthesis Scripts (for ASIC), User Constraint File (for FPGA)
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