ASIC Architect, Inc. 
Short Desc. : PCI Express Dual Mode Cores
Overview :
ASIC Architect's high performance cores come in multiple datapath flavors with the choice of 8-bit or 16-bit PIPE PHY Interface. The cores have been architected to achieve very low latency, high throughput, and quick timing closure with a very small silicon footprint. The user interface provides practical and integration-friendly mechanisms for the integration of the cores to the user logic.
Features : - High Performance with Low Latency, Maximum Throughput, Multiple Pipelined Memory WR/RD capability
- Low Silicon Footprint - Suitable for Multiple Instances of the Core in Single ASIC/FPGA
- Highly Parameterized Core supporting both cut-through and store-and-forward schemes
- Supports operation with 8-bit and 16-bit PIPE interface
- Implements all optional configuration space and capability structures
- Configurable Retry buffering scheme for low footprint and latency
- Supports all power management states L0,L0s,L1,L2 & L3
- Supports PCI Express Advanced Error Reporting
Categories :
Portability :
Type : Soft
Deliverables : - Synthesizable Verilog RTL, Testbench and Models for Simulation, Sample Synthesis Scripts (for ASIC), User Constraint File (for FPGA)
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy