Faraday Technology Corp. 
Part Number : FSA0A_C_SW
Overview :
The FSA0A_C_SW is a low power, synchronous, two-port SRAM. It is implemented
according to UMC’s 0.18μm technology and can be incorporated with Faraday’s
0.18μm standard cells. Different combinations of words, bits, and aspect ratios can be
used to generate the most desirable configuration.
By requesting the desired size and timing constraints, the FSA0A_C_SW compiler is
capable of providing suitable synchronous RAM layout instances in minutes. It also
automatically generates data sheets, Verilog behavioral simulation models, SCS and
Viewlogic symbols, place & route models and test patterns for use in ASIC designs.
After the setup / hold time and minimum high / low pulse width are satisfied, the duty
cycle length can be neglected to allow a flexible clock falling edge during each
operation. Both word write and byte write operations are supported.
Features : - Operating voltage range: 1.62V ~1.98V
- Operating junction temp. range: 0°C ~ 115°C
- Recommended operating ambient temp. range: 0°C ~ 85°C
- Minimum metal requirement: 4 metal layers
- Synchronous read and write operation
- One (1) read port and one (1) write port
- Fully customized layout density
- Fully synchronous independent operation for each port
- Fully static operation, no DC current
- Clocked address inputs for read port and write port into RAM with CKA and CKB rising edges
- Clocked WEB into RAM with CKB rising edge
- Clocked DI inputs into RAM with CKB rising edge
- Byte write and word write operations available
- Different aspect ratios to best fit chip floorplan
- Variable capacity: maximum 36K bits
- Tri-state output buffer
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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