Short Desc. : DDR3 SDRAM Controller Core
Overview :
Northwest Logic’s Double Data Rate 3 (DDR3) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and translates them to the command sequences required by DDR3 SDRAM devices. The core also performs all initialization and refresh functions.
Features : - High memory throughput achieved via Look-Ahead command processing,
- Bank Management, Auto-Precharge and Additive Latency support
- Multi-Port Front-End supports high efficiency command reordering and multi-port interface
- ECC, RMW, and Multi-Burst add-on modules available
- Achieves high clock rates with minimal routing constraints
- Supports all JEDEC standard DDR3 SDRAM chips and DIMMs
- Run-time configurable timing parameters and memory settings
- A variety of read capture options are supported
- Full support of ODT and 2T timing
- Automatic generation of initialization and refresh sequences
- Supports self-refresh and powerdown modes
- Source code available
- Customization and Integration services available
Categories :
Portability :
Type : Soft
Deliverables : - Core (Netlist or Source Code), Comprehensive Verification Suite (Source Code), Complete Documentation, Expert Technical Support & Maintenance Updates
S2C: FPGA Base prototyping- Download white paper

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