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 ASIC IP 
Short Desc. : PCI Core
Overview :
The PCI Core implements the “front-end” of a PCI design giving the user complete control of the “back-end” functionality. This flexibility is further enhanced with a user expandable configuration space. This PCI Core supports automatic loading of
the configuration space via a EEPROM.
Features : - High-performance, easy-to-use core
- Achieves push-button timing with minimal routing constraints
- Minimal size
- Supports 33/66 MHz, 32/64 bit operation
- Master/Target and Target-Only versions available
- Host and Peripheral versions available
- User expandable configuration space can be loaded from EEPROM
- Provided with a comprehensive Verification Suite
- Optional Scatter-Gather DMA Module available
- Source code available
- Customization and Integration services available
- PCI Local Bus Specification Revision 3.0 compliant
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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