Faraday Technology Corp. 
Part Number : FS80A_B_SB
Overview :
The FS80A_B_SB is a high density, synchronous, two-port SRAM. It is implemented
according to UMC’s 0.35μm technology. Different combinations of words, bits, and aspect
ratios can be used to generate the most desirable configuration.
By requesting for the desired size and timing constraints, the FS80A_B_SB compiler is capable
of providing suitable synchronous SRAM layout instances in minutes. It also automatically
generates data sheets, Verilog behavioral simulation models, SCS and Viewlogic symbols, place
& route models and test patterns for use in ASIC designs. The duty cycle length can be
neglected as long as the setup / hold time and minimum high / low pulse width are satisfied,
which allows a flexible clock falling edge during each operation. Both word write and byte
write operations are supported.
Features : - Operating voltage range: 3.0V ~3.6V
- Operating junction temp. range: 0°C ~ 115°C
- Recommended operating ambient temp. range: 0°C ~ 85°C
- Minimum metal requirement: 3 metal layers
- Synchronous read and write operation
- One (1) read port and one (1) write port
- High density, fully customized layout density
- Fully synchronous independent operation for each port
- Automatic power down mechanism to eliminate operating current
- Clocked address inputs for read port and write port into RAM with rising CKA and CKB edges
- Clocked WEB into RAM with rising CKB edge
- Clocked DI inputs into RAM with rising CKB edge
- Byte write and word write operations available
- Optional aspect ratios to best fit chip floorplan
- Variable capacity: maximum 160K bits
- Tri-state output buffer
Categories :
Portability :
Type : Hard
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

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