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XAP3 is a 32-bit RISC processor designed for low cost, low power ASICs with a high computation requirement. It has powerful support for C programming, operating systems and features for secure code execution with excellent software portability and fast interrupt response. The processor hardware is optimised for systems using Flash memory for program storage.
- Soft IP core with royalty free licensing model
- Byte addressable flat 4 GB memory space with unaligned memory access for high data density
- High code density using freely mixed 16- and 32-bit instructions
- Two- or three-stage pipeline hardware versions
- High performance up to 0.76 DMIPS/MHz with two-stage pipeline XAP3a
- Fast clock up to 180 MHz on 90 nm with three-stage pipeline XAP3b
- Smallest version XAP3a occupies just 30k gates
- Low 80 uW/MHz dynamic power on 90 nm
- Powerful 175 RISC instruction set
- 16 processor registers and 16 debug registers
- Protected operating modes for user, supervisor, interrupt and NMI code
- Selected multi-cycle instructions accelerate block copy, string handling, multiply, divide, function entry and exit
- Von Neumann architecture for unified memory system
- Processor sleep mode for low power
- Integrated SIF debug for non-invasive, real-time access to processor and memory mapped devices over a four-wire interface
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