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Short Desc. : Serial ATA I/II Host Controller IP Core
Overview :
The Serial ATA Host Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.
Features : - 10 bit Phy interface
- Connects to SAPIS compliant serial ATA Phy
- Fully compliant to SATA Gen 1(1.2 Gb/s) and Gen 2 (2.4 Gb/s)
- Wishbone slave interface for register access and FIFO/DMA data transfers
- Only very few FF's in the Phy clock domain, main part on the Wishbone clock
- 128 byte (32 double word) data FIFO (optional 256 byte)
- Implements the shadow register block and the serial ATA status and control registers
- Parallel ATA legacy software compatibility
- 48-bit address feature set supported
- Master only emulation (supports 1 device)
- 8b/10b coding and decoding
- CONT and data scramblers to reduce EMI
- CRC generation and checking
- Auto inserted HOLD primitives
- Power management support (partial and slumber)
- Optional native mode programming model
- Many configuration options
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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