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Short Desc. : Reed Solomon Decoder IP Core
Overview :
This high performance, fully programmable Reed Solomon Decoder IP Core is intended for use in a wide range of applications requiring forward error correction and can be targeted in any ASIC or FPGA technologies. In channel coding redundancy is inserted in the transmitted information bit-stream.
Features : - Continuous, very high-speed, time-domain Reed-Solomon decoding algorithm.
- Supports different Reed-Solomon coding standards.
- Supports error and erasure decoding
- Code rate can be dynamically varied
- Parameterizable bits per symbol (M).
- Programmable codeword length (NVAL) with parameterizable maximum value (N).
- Programmable number of errors (TVAL) with parameterizable maximum value (T).
- Shortened codes supported (NVAL,TVAL).
- User configured primitive field polynomial.
- User configured generator polynomial.
- Synchronous design.
- Predictable decoder latency.
- Single or Multiple symbol rate clock (CR).
- Status and performance monitoring signals
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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