ASICS World Services, LTD. 
Short Desc. : MMC Device IP Core
Overview :
A compact low power and scalable IP core which provides a simple, firmware-friendly cost-effective Physical Link interface for MultiMediaCard-based
memory and i/o devices, such as MMC memory cards, MMC-RS, MMC-Mobile, CE-ATA devices etc.
Features : - Compliant with MultiMediaCard Spec ver4.X/3.X
- Supports MMC 1bit, 4bit, 8bit modes, as well as SPI mode
- Maximum data rate up to 416Mbits/sec
- All command and response types are supported
- Supports Interrupt-mode (Wait-IRQ)
- Supports CEATA specifications (ver1.0), including Completion Signal
- Generic 8/16/32 bit system bus interface
- Optional extended data buffering 0-4K bytes.
- Optional read/write data DMA
- Card-Busy signal asserted by hardware, negated by firmware
- CRC7 and CRC16 checksum logic
- Supports data block size of 1 byte to 4K bytes
- Set of “Read-Clear” status bits with software interrupt mask
- Multi-block read and write
- Stream read and write
- Built-in Bus Test Procedure
- Supports fast and slow cards. MMC clock frequency: 0-52+MHz
- Supports MMC clock suspension
- Supports hot card insertion and removal
- Compact and trivial firmware interface
Categories :
Portability :
Type : Soft
S2C: FPGA Base prototyping- Download white paper

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