ASICS World Services, LTD. 
Short Desc. : SD/SDIO Device IP Core
Overview :
A compact low power and scalable IP core which provides a simple, firmware-friendly cost-effective Physical Link interface for memory, i/o and combo
devices, such as SD-based memory cards, Mini SD, Micro SD, SDIO Bluetooth devices, SDIO GPS, etc.
Features : - Compliant with SD Spec ver1.10 and SDIO Spec ver1.10
- Supports SD 1bit and 4bit modes, as well as SPI mode
- 8bit support for future SD spec enhancements
- Supports SDIO features: Suspend/Resume, Interrupt, Read Wait
- All command and response types are supported
- Generic 8/16/32 bit system bus interface
- Set of “Read-Clear” status bits with interrupt mask
- Optional extended data buffering 0-4K bytes.
- Optional read/write data DMA
- Busy signal asserted by hardware, negated by firmware
- CRC7 and CRC16 checksum logic
- Supports data block size of 1 byte to 4K bytes
- Multi-block read and write
- Supports fast and slow cards. SD clock frequency: 0-50+MHz
- Supports SD clock suspension
- Supports hot card insertion and removal
- Compact and trivial firmware interface
Categories :
Portability :
Type : Soft
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper

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