Aurora VLSI Inc 
Short Desc. : AU-B3000: AMBA AHB Bus Master Core
Overview :
The AU-B3000 AMBA AHB Bus Master provides the bus master function for the AMBA AHB
Bus. It accepts requests from the user’s logic and turns them into AMBA Bus transactions on the AMBA AHB Bus. The AMBA AHB Bus Master is available as a synthesizable Verilog model from Aurora VLSI, Inc.
Features : - AMBA AHB Bus master function
- 32 bit or 64 bit AMBA AHB Bus- user configurable
- Fully pipelined for highest throughput
- Supports all required AMBA AHB Bus features
- Simple request/acknowledge and valid/ready requester interface protocols
- Write abort to terminate writes early
- AMBA Bus read error returned to the user with the read data
- Big endian and little endian modes
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes
S2C: FPGA Base prototyping- Download white paper

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