Aurora VLSI Inc 
Short Desc. : AU-S1000: Processor Memory and Bus Interface Core
Overview :
The AU-S1000 Processor Memory and Bus Interface Core provides system interfaces for Aurora VLSI processors including the AU-C01XX Processor Core family, AU-J1XXX Java Core family, and AU-J2XXX Java Core family. In an SOC, it connects the Processor Core to the memory system that may include RAM, a system bus, and on-chip control and status registers. The AUS1000 Processor Memory and Bus Interface Core is available as synthesizable Verilog models from Aurora VLSI, Inc.
Features : - Memory and bus interface supporting Aurora VLSI Processor Cores
- AU-C01XX 32 Bit, Tiny, Low Power Processor Cores
- AU-JXXXX Java Processor Cores
- Seamless connection to Aurora VLSI Processor Cores
- Memory system requests from the Processor Core on two independent request
- interfaces
- instruction request interface
- data request interface
- Determines the memory request target:
- RAM memory
- System bus peripheral device
- On-chip register
- Drives the request to the memory request target
- Receives read data and error information from the request target
- Passes read data and error information back to the Processor Core
- Signals memory system wait cycles to the Processor Core as needed
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes

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