|The FSA0A_C_SC is a Via2 programmable, synchronous ROM. It is implemented according to UMC’s 0.18μm 1P5M technology and can be incorporated with Faraday’s 0.18μm standard cells. Different combinations of words, bits, and aspect ratios can be used to generate the most desirable configurations.
By requesting the desired size and timing constraints, the FSA0A_C_SC compiler is capable of providing suitable synchronous ROM layout instances in minutes. The FSA0A_C_SC automatically generates data sheets, Verilog behavioral simulation models, SCS or Viewlogic symbols, place & route models and test patterns for use in