Aurora VLSI Inc 
Short Desc. : AU-MB1000: SRAM Controller AMBA Subsystem Core
Overview :
The AU-MB1000 SRAM Controller AMBA Subsystem provides an SRAM Controller peripheral subsystem for AMBA based SOCs. It contains an SRAM Controller that connects seamlessly to the AMBA AHB Bus as an AMBA Bus slave. The SRAM Controller AMBA Subsystem Core is available as a synthesizable Verilog model from Aurora VLSI, Inc.
Features : - SRAM Controller
- Supports several SRAM types- flow through ZBT synchronous, pipelined ZBT
- synchronous, flow through syncburst synchronous, SCD syncburst synchronous, DCD syncburst synchronous, and asynchronous SRAMs
- 32 bit or 64 bit SRAM data bus
- 512 Kbyte to 512 Mbyte SRAM memory system
- Pipelined accesses for highest performance
- 0, 1, or 2 cycle read latency
- 0, 1, or 2 cycle write latency
- 1, 2, or 4 banks of SRAM
- 17 to 24 address bits
- SRAM powerdown supported
- AMBA Slave Interface
- AMBA AHB Bus slave
- 32 bit or 64 bit AMBA AHB Bus- user configurable
- Supports all required AMBA AHB Bus features
- Implements AMBA Bus timeout and RETRY response
- Read data prefetching
- Write data packing
- Same cycle device request/response is supported for highest throughput
- Handles all data packing/unpacking and data alignment for data transfer sizes that do not match the AMBA Bus width and/or SRAM data bus width
- User configurable for big or little endian AMBA Bus and memory
- AMBA Bus and SRAM interface can be asynchronous to each other
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes

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