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 Aurora VLSI Inc 
Short Desc. : AU-M2300: SDRAM/DDR/DDR2 Controller Core
Overview :
The AU-M2300 SDRAM/DDR/DDR2 Controller Core is a pipelined, high performance
SDRAM, DDR, and DDR2 SDRAM controller. Software configures the SDRAM/DDR/DDR2
Controller for one of SDRAM, DDR, or DDR2 SDRAM accesses. The SDRAM/DDR/DDR2
SDRAM data bus width is user configurable to 32 or 64 bits. The SDRAM/DDR/DDR2
Controller supports SDRAM, DDR, and DDR2 SDRAM memory systems from 4 Mbytes to 4
Gbytes. SDRAM/DDR/DDR2 SDRAM timing parameters are software programmable to support a wide range of SDRAM, DDR, and DDR2 SDRAM speed grades and clock frequencies.
Features : - 32 bit or 64 bit SDRAM/DDR/DDR2 SDRAM data bus
- 4 Mbyte to 4 Gbyte SDRAM/DDR/DDR2 memory system
- Pipelined accesses to active rows for highest performance
- 1, 2, or 4 banks of SDRAM/DDR/DDR2 SDRAMs
- SDRAM/DDR/DDR2 SDRAM powerdown supported
- Fully programmable SDRAM/DDR/DDR2 SDRAM timing parameters
- Auto-refresh with programmable SDRAM/DDR/DDR2 SDRAM refresh interval
- SDRAM
- 2 or 3 cycle CAS latency
- 2 or 4 SDRAM internal banks
- 8, 9, 10, 11, or 12 column address bits
- 11, 12, or 13 row address bits
- DDR
- 2, 2.5, or 3 cycle CAS latency
- 4 DDR SDRAM internal banks
- 9, 10, 11, or 12 column address bits
- 12, 13, or 14 row address bits
- DDR2
- 3, 4, or 5 cycle CAS latency
- 4 or 8 SDRAM/DDR/DDR2 SDRAM internal banks
- 9, 10, 11, or 12 column address bits
- 13 or 14 row address bits
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes
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