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 Aurora VLSI Inc 
Short Desc. : AU-M2000: SDRAM Controller Core
Overview :
The AU-M2000 SDRAM Controller Core is a pipelined, high performance SDRAM controller. The SDRAM data bus width is user configurable to 32 or 64 bits. The SDRAM Controller supports SDRAM memory systems from 4 Mbytes to 4 Gbytes. SDRAM timing parameters are software programmable to support a wide range of SDRAM speed grades and clock frequencies. Refresh is initiated by the SDRAM Controller according to the software programmable refresh interval. To conserve power the SDRAMs can be put in low power mode. The SDRAM Controller is available as a synthesizable Verilog model from Aurora VLSI, Inc.
Features : - 32 bit or 64 bit SDRAM data bus
- 4 Mbyte to 4 Gbyte SDRAM memory system
- Pipelined accesses to active rows for highest performance
- 2 or 3 cycle CAS latency
- 1, 2, or 4 banks of SDRAM
- 2 or 4 SDRAM internal banks
- 8, 9, 10, 11, or 12 column address bits
- 11, 12, or 13 row address bits
- SDRAM powerdown supported
- Fully programmable SDRAM timing parameters
- Auto-refresh with programmable SDRAM refresh interval
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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