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 Aurora VLSI Inc 
Short Desc. : AU-FB8010: IEEE 1394a AMBA Subsystem Core
Overview :
The AU-FB8010 IEEE 1394a AMBA Subsystem provides an IEEE 1394a peripheral subsystem for AMBA based SOCs. It contains an IEEE 1394a Link Layer Controller that connects seamlessly to the AMBA AHB Bus. A DMA Engine is included to move packet data. The figure below shows its use within an SOC. The IEEE 1394a AMBA Subsystem Core is available as a synthesizable Verilog model from Aurora VLSI, Inc.
Features : - IEEE 1394a Link Layer Controller
- Compliant with IEEE 1394a
- IEEE 1394a link layer functionality
- IEEE 1394a-2000 PHY interface and IEEE 1394-1995 Annex J.PHY interface
- Supports 100, 200, and 400 mbits/s
- Cycle master capability
- Generates CRC for transmit and checks CRC for receive packets
- Asynchronous and isochronous transfers are supported
- Separate transmit data FIFOs for asynchronous and isochronous packets
- Receive data FIFO for incoming packets
- Packet status captured in 2 status FIFOs
- Transmit Status FIFO- 4 entries
- Receive Status FIFO- 4 entries
- PHY status and cycle sync status are provided
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes
S2C: FPGA Base prototyping- Download white paper



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