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 Aurora VLSI Inc 
Short Desc. : AU-NB8800: Ethernet 10/100/1000 AMBA Subsystem Core
Overview :
The AU-NB8800 Ethernet 10/100/1000 AMBA Subsystem provides an Ethernet 10/100/1000 peripheral subsystem for AMBA based SOCs. It contains an Ethernet 10/100/1000 MAC that connects seamlessly to the AMBA AHB Bus. A DMA Engine is included to move Ethernet frame data. The figure below shows its use within an SOC. The Ethernet 10/100/1000 AMBA Subsystem Core is available as a synthesizable Verilog model from Aurora VLSI, Inc.
Features : - Ethernet 10/100/1000 MAC
- 10mb/s, 100mb/s, or 1000mb/s Ethernet line speeds
- Industry standard MII, GMII, RGMII, and TBI interfaces to the PHY
- IEEE 802.3z compliant (1000mb/s)
- Full and half duplex
- Supports full duplex flow control (IEEE 802.3x)
- Automatic retries after collision, programmable retry counter
- Automatic padding and removal of PAD bytes to meet minimum frame size
- FCS generation for transmitted packets, and checking on received packets
- Supports carrier extension and packet bursting
- Includes PCS block for SERDES interface to optical Gigabit PHY
- MDIO interface for PHY management
- Programmable address filtering
- Frame status captured in 2 status FIFOs
- Transmit Status FIFO- 4 entries
- Receive Status FIFO- 4 entries
- 256 to 8192 byte Transmit FIFO
- 256 to 8192 byte Receive FIFO
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes
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