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 Aurora VLSI Inc 
Short Desc. : AU-G0700: Reset Controller AMBA APB Core
Overview :
The AU-G0700 Reset Controller AMBA APB Core provides a reset controller peripheral for AMBA based SOCs. It aggregates two pin resets, two interrupt/watchdog resets, and software reset capabilities into 32 individual reset signals for use throughout an SOC. It connects seamlessly to the AMBA APB Bus as an AMBA Bus slave. The Reset Controller AMBA APB Core is available as a synthesizable Verilog model from Aurora VLSI, Inc.
Features : - Up to 32 reset outputs (configurable)- asserted high or low (configurable)
- Configurable reset de-assertion delay up to 64K cycles for each reset output
- 2 pin reset requests
- nonmaskable
- asynchronously asserted, synchronously de-asserted
- asserted high or low (configurable)
- 2 interrupt/watchdog reset requests
- individually maskable for each reset output
- synchronously asserted, synchronously de-asserted
- asserted high or low (configurable)
- Software reset requests
- individually asserted by software for each reset output
- synchronously asserted, synchronously de-asserted
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes
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