Aurora VLSI Inc 
Short Desc. : AU-B1000: AMBA AHB Bus Arbiter and Decoder Core
Overview :
The AU-B1000 AMBA AHB Bus Arbiter and Decoder provides the bus arbiter and slave select decoder for the AMBA AHB Bus. It is fully pipelined for highest throughput and performance. The full set of sixteen AMBA Bus masters and sixteen AMBA Bus slaves is supported. The AMBA AHB Bus Arbiter/Decoder is available as a synthesizable Verilog model from Aurora VLSI, Inc.
Features : - AMBA AHB Bus arbiter function
- AMBA AHB Bus decoder function
- 16 AMBA Bus masters
- 16 AMBA Bus slaves
- Fully pipelined for highest throughput
- Round robin arbitration
- 16 slave address registers- one register per slave
- Base address of the slave’s address space
- Size of the slave’s address space
- Default master- Master 0
- Default slave- Slave 0
- User can optionally supply the default master and/or default slave
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes
CST: Webinars Begin on February 9
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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