Aurora VLSI Inc 
Short Desc. : AU-B0001: AMBA AHB/APB Bus Bridge Core
Overview :
The AMBA AHB/APB Bus Bridge is a bridge between an AMBA AHB Bus and an AMBA APB
Bus. It includes the slave select line decoder for the AMBA APB Bus. Sixteen AMBA APB Bus slaves are supported. The AMBA AHB/APB Bus Bridge is available as a synthesizable Verilog model from Aurora VLSI, Inc.
Features : - AMBA AHB Bus to APB Bus bridge function
- AMBA APB Bus decoder function
- 16 AMBA APB Bus slaves
- Supports all AMBA AHB Bus transaction types
- Supports all AMBA AHB Bus burst types
- Supports AMBA AHB data sizes of 1, 2, and 4 bytes
- 16 slave address registers- one register per slave
- base address of the slave’s address space
- size of the slave’s address space
- Synchronous or asynchronous AMBA AHB bus clock and AMBA APB bus clock
Categories :
Portability :
Type : Soft
Deliverables : - RTL Verilog source code model of the core, Verilog testbench and test cases, Synthesis scripts examples, Complete detailed documentation and training class notes
S2C: FPGA Base prototyping- Download white paper

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