Faraday Technology Corp. 
Part Number : FTPCIXP100
Overview :
Faraday’s FTPCIXP100 is a PCI Express controller that is compliant with the PCI express base specification 1.1. The FTPCIXP100 implements a general-purpose application interface which can be used to transfer the packets between the application and internal FIFOs. If the requester is implemented, the user can actively transfer the packets into FIFO via the transmitting interface and receive the packets from FIFO via the receiving interface. If the completer is implemented, the user can wait for the requested packets via the receiving interface and transmit the completion packets via the transmitting interface. The FTPCIXP100 supports the 16-bit PIPE interface to the transceiver up to x4 link width. It can initialize the link and decide the link characteritics during the link training. 2 clock domains exist in the FTPCIXP100. One is for the 64-bit application interface that ranges from 33 MHz to 133 MHz and the other is for the PIPE clock at 125 MHz.
Features : - Compliant with PCI Express base specification 1.1
- Supports the 16-bit PIPE (PHY interface)
- Provides the 64-bit application interface (Larger than 1G bytes/sec at 133 MHz in one direction)
- Supports the PCI Express layered architecture (Transaction, data-link, and physical layers)
- Transmit/Receive flow control
- Supports the PCI Express native power management
- Supports the multiple lanes up to x 4
- Automatic link width negotiation
- Supports the lane number and lane polarity reversal
- Maximum payload size up to 4K bytes
- Supports the single Virtual Channel (VC0)
- Supports the multiple traffic class (TC0 ~ TC7)
- Supports the single function
- Supports 6 BAR
- Supports the I/O and Memory BAR
- The BAR setting can be changed by application
- Supports the legacy interrupt (INTA)
- Supports MSI (MSI-X is not supported)
- Supports different clock rates for application interface and PHY
- Configurable TX/RX FIFO sizes
Categories :
Portability :
Type : Soft

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